SDNoC 42: modelo de SDNoC baseada em otimização de caminhos mínimos
In this work, we developed a new network-on-chip architecture using softwaredefined networks; this architecture proved to be robust and capable of improving routing in a network-on-chip. The implementation consists of a software-defined network-on-chip architectural model, exploring the parallelis...
Na minha lista:
| Autor principal: | |
|---|---|
| Outros Autores: | |
| Formato: | Dissertação |
| Idioma: | pt_BR |
| Publicado em: |
Universidade Federal do Rio Grande do Norte
|
| Assuntos: | |
| Endereço do item: | https://repositorio.ufrn.br/handle/123456789/57146 |
| Tags: |
Adicionar Tag
Sem tags, seja o primeiro a adicionar uma tag!
|
| Resumo: | In this work, we developed a new network-on-chip architecture using softwaredefined networks; this architecture proved to be robust and capable of improving
routing in a network-on-chip. The implementation consists of a software-defined
network-on-chip architectural model, exploring the parallelism of control mechanisms using Dijkstra’s algorithm to find the best path in packet routing between switches. The approach proposes a significant improvement in communication latency by reducing the waiting time of packets in the controllers’
queue and exploring the network’s topological potential through the OpenFlow
protocol. The results obtained are promising. Using the Dijkstra algorithm and
increasing the number of cores makes optimizing communication latency in
100% of cases possible compared to the XY algorithm. |
|---|