Injeção de falhas e verificação de hardware para o CEVERO

CEVERO is a processor developed by LAPPS, a laboratory at the Universidade Federal do Rio Grande do Norte. It was developed aiming to be fault tolerant using hardware redundancy technique, having two Ibex cores, which are based in the RISC-V architecture. With the aim of validate the reliability...

ver descrição completa

Na minha lista:
Detalhes bibliográficos
Autor principal: Dantas, Matheus Luna de Oliveira
Outros Autores: Souza, Samuel Xavier de
Formato: bachelorThesis
Idioma:pt_BR
Publicado em: Universidade Federal do Rio Grande do Norte
Assuntos:
Tolerância a falhas
Injeção de falhas
Simulação
SEU
RISC-V
CEVERO
CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO::HARDWARE
Endereço do item:https://repositorio.ufrn.br/handle/123456789/53656
Tags: Adicionar Tag
Sem tags, seja o primeiro a adicionar uma tag!
Descrição
Resumo:CEVERO is a processor developed by LAPPS, a laboratory at the Universidade Federal do Rio Grande do Norte. It was developed aiming to be fault tolerant using hardware redundancy technique, having two Ibex cores, which are based in the RISC-V architecture. With the aim of validate the reliability of CEVERO, it will be used fault injection techniques, writing testbenches in SystemVerilog and simulating them in ModelSim, modeling an environment that can simulate some effects caused by radiation, such as Single Event Upsets (SEU). This proccess of validation through fault injections is proposed to be just the beginning of a future complete hardware verification environment for CEVERO. It was possible to verify that CEVERO keep resilient to failure, proving its reability.

Registros relacionados