Analytical speedup modeling for parallel applications with variable memoryaccess delay in symmetric architectures

Several analytical models created since Amdahl’s pioneering work have explored aspects such as variation in the size of the problem, memory size, communication overhead, and synchronization overhead. However, delays in memory access are considered constant. Such delays can vary, for example, accord...

সম্পূর্ণ বিবরণ

সংরক্ষণ করুন:
গ্রন্থ-পঞ্জীর বিবরন
প্রধান লেখক: Furtunato, Alex Fabiano de Araújo
অন্যান্য লেখক: Souza, Samuel Xavier de
বিন্যাস: doctoralThesis
ভাষা:pt_BR
প্রকাশিত: Universidade Federal do Rio Grande do Norte
বিষয়গুলি:
Analytical modeling
Speedup modeling
Parallel systems
Data access delay
Speedup
Memory wall
অনলাইন ব্যবহার করুন:https://repositorio.ufrn.br/handle/123456789/32749
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id ri-123456789-32749
record_format dspace
institution Repositório Institucional
collection RI - UFRN
language pt_BR
topic Analytical modeling
Speedup modeling
Parallel systems
Data access delay
Speedup
Memory wall
spellingShingle Analytical modeling
Speedup modeling
Parallel systems
Data access delay
Speedup
Memory wall
Furtunato, Alex Fabiano de Araújo
Analytical speedup modeling for parallel applications with variable memoryaccess delay in symmetric architectures
description Several analytical models created since Amdahl’s pioneering work have explored aspects such as variation in the size of the problem, memory size, communication overhead, and synchronization overhead. However, delays in memory access are considered constant. Such delays can vary, for example, according to the number of cores, the relationship between the processor and memory frequencies, and the problem size. Given different problem sizes and many possible configurations of operational frequency and number of cores that current architectures can offer, speedup models suitable for describing such differences are quite desirable for either offline or online scheduling decisions. This thesis presents a novel analytical speedup model that considers variations in the average data-access delay to describe the limiting effect of the memory wall in parallel applications associated with homogeneous shared memory architectures. The experimental results indicate that the proposed model incorporates the behavior of the application adequately. The approach presented in this work shows that considering parameters that reflect the intrinsic characteristics of applications has advantages over statistical models such as those based on machine learning. The experiments also show that the conventional machine learning modeling may require measurements with one order of magnitude above to achieve the same accuracy level when compared with the proposed model.
author2 Souza, Samuel Xavier de
author_facet Souza, Samuel Xavier de
Furtunato, Alex Fabiano de Araújo
format doctoralThesis
author Furtunato, Alex Fabiano de Araújo
author_sort Furtunato, Alex Fabiano de Araújo
title Analytical speedup modeling for parallel applications with variable memoryaccess delay in symmetric architectures
title_short Analytical speedup modeling for parallel applications with variable memoryaccess delay in symmetric architectures
title_full Analytical speedup modeling for parallel applications with variable memoryaccess delay in symmetric architectures
title_fullStr Analytical speedup modeling for parallel applications with variable memoryaccess delay in symmetric architectures
title_full_unstemmed Analytical speedup modeling for parallel applications with variable memoryaccess delay in symmetric architectures
title_sort analytical speedup modeling for parallel applications with variable memoryaccess delay in symmetric architectures
publisher Universidade Federal do Rio Grande do Norte
publishDate 2021
url https://repositorio.ufrn.br/handle/123456789/32749
work_keys_str_mv AT furtunatoalexfabianodearaujo analyticalspeedupmodelingforparallelapplicationswithvariablememoryaccessdelayinsymmetricarchitectures
_version_ 1773958341404393472
spelling ri-123456789-327492021-06-21T23:04:01Z Analytical speedup modeling for parallel applications with variable memoryaccess delay in symmetric architectures Furtunato, Alex Fabiano de Araújo Souza, Samuel Xavier de http://lattes.cnpq.br/9659861253244985 http://lattes.cnpq.br/9892239670106361 Silveira, Luiz Felipe de Queiroz http://lattes.cnpq.br/4139452169580807 Silva, Ivanovitch Medeiros Dantas da http://lattes.cnpq.br/3608440944832201 Lorenzon, Arthur Francisco http://lattes.cnpq.br/2890260984567329 Borin, Edson http://lattes.cnpq.br/4176915322233893 Analytical modeling Speedup modeling Parallel systems Data access delay Speedup Memory wall Several analytical models created since Amdahl’s pioneering work have explored aspects such as variation in the size of the problem, memory size, communication overhead, and synchronization overhead. However, delays in memory access are considered constant. Such delays can vary, for example, according to the number of cores, the relationship between the processor and memory frequencies, and the problem size. Given different problem sizes and many possible configurations of operational frequency and number of cores that current architectures can offer, speedup models suitable for describing such differences are quite desirable for either offline or online scheduling decisions. This thesis presents a novel analytical speedup model that considers variations in the average data-access delay to describe the limiting effect of the memory wall in parallel applications associated with homogeneous shared memory architectures. The experimental results indicate that the proposed model incorporates the behavior of the application adequately. The approach presented in this work shows that considering parameters that reflect the intrinsic characteristics of applications has advantages over statistical models such as those based on machine learning. The experiments also show that the conventional machine learning modeling may require measurements with one order of magnitude above to achieve the same accuracy level when compared with the proposed model. Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES Vários modelos analíticos criados desde o trabalho pioneiro de Amdahl exploraram aspectos tais como variação no tamanho do problema, tamanho da memória, sobrecarga de comunicação e sobrecarga de sincronização. Contudo, atrasos no acesso à memória são considerados constantes. Esses atrasos podem variar, por exemplo, de acordo com o número de núcleos usados, a relação entre as frequências do processador e da memória e o tamanho do problema. Dado os diferentes tamanhos de problemas e o grande número de configurações possíveis de frequência operacional e número de núcleos que as arquiteturas atuais podem oferecer, modelos de speedup adequados para descrever tais variações entre essas configurações são bastante desejáveis para decisões de escalonamento offline ou online. Esta tese apresenta um novo modelo analítico de speedup que considera variações no atraso médio de acesso à memória para descrever o efeito limitador da barreira de memória em aplicações paralelas em arquiteturas homogêneas de memória compartilhada. Os resultados experimentais indicam que a modelagem proposta captura bem o comportamento da aplicação. A proposta apresentada nesse trabalho mostra que incorporar parâmetros que refletem as características intrínsecas das aplicações tem vantagens sobre modelos estatísticos como os baseados em aprendizagem de máquina. Os experimentos também mostram que a modelagem de aprendizagem de máquina convencional pode precisar de uma ordem de magnitude a mais de medições para atingir o mesmo nível de acurácia em comparação com o modelo proposto. 2021-06-21T23:03:10Z 2021-06-21T23:03:10Z 2021-02-09 doctoralThesis FURTUNATO, Alex Fabiano de Araújo. Analytical speedup modeling for parallel applications with variable memoryaccess delay in symmetric architectures. 2021. 125f. Tese (Doutorado em Engenharia Elétrica e de Computação) - Centro de Tecnologia, Universidade Federal do Rio Grande do Norte, Natal, 2021. https://repositorio.ufrn.br/handle/123456789/32749 pt_BR Acesso Aberto application/pdf Universidade Federal do Rio Grande do Norte Brasil UFRN PROGRAMA DE PÓS-GRADUAÇÃO EM ENGENHARIA ELÉTRICA E DE COMPUTAÇÃO

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