Hardware strategies applied to the latency reduction on tactile internet
This work proposes to present hardware strategies applied to reduce latency in the tactile internet. The motivation is to study the challenges contained in the development of the hardware associated with the tactile devices, especially issues related to the round trip latency limit of the system...
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Internet tátil Redução de latência Dispositivo háptico Computação reconfigurável FPGA |
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Internet tátil Redução de latência Dispositivo háptico Computação reconfigurável FPGA Silva Júnior, José Cláudio Vieira e Hardware strategies applied to the latency reduction on tactile internet |
| description |
This work proposes to present hardware strategies applied to reduce latency in the
tactile internet. The motivation is to study the challenges contained in the development of
the hardware associated with the tactile devices, especially issues related to the round trip
latency limit of the system components. As is known, for a tactile internet environment
to work desirably, it is necessary to respect a minimum limit of round trip latency. Since
some tactile applications allow some human senses to interact with the machines remotely,
this means that, almost always, the minimum limit of round trip latency has a time delay
in the range of milliseconds. Thus, it is clear that there is a demand for tactile devices that
are quite fast. In this context, three hardware proposals are presented that have the main
objective to reduce the total latency produced by this type of device. The first strategy
proposed for the development of hardware is to use reconfigurable computing (on FPGA)
to minimize the execution time of the algorithms associated with the device. The second
hardware proposal also makes use of reconfigurable computing (on FPGA). However, the
hardware is designed using another type of numerical representation. Finally, the third
proposal presents a tactile glove model implemented using a variety of micro processed
system. Results associated with the three proposals are presented and show the viability
of the strategies, presenting better performance concerning the works that were compared. |
| author2 |
Fernandes, Marcelo Augusto Costa |
| author_facet |
Fernandes, Marcelo Augusto Costa Silva Júnior, José Cláudio Vieira e |
| format |
doctoralThesis |
| author |
Silva Júnior, José Cláudio Vieira e |
| author_sort |
Silva Júnior, José Cláudio Vieira e |
| title |
Hardware strategies applied to the latency reduction on tactile internet |
| title_short |
Hardware strategies applied to the latency reduction on tactile internet |
| title_full |
Hardware strategies applied to the latency reduction on tactile internet |
| title_fullStr |
Hardware strategies applied to the latency reduction on tactile internet |
| title_full_unstemmed |
Hardware strategies applied to the latency reduction on tactile internet |
| title_sort |
hardware strategies applied to the latency reduction on tactile internet |
| publisher |
Universidade Federal do Rio Grande do Norte |
| publishDate |
2020 |
| url |
https://repositorio.ufrn.br/jspui/handle/123456789/30106 |
| work_keys_str_mv |
AT silvajuniorjoseclaudiovieirae hardwarestrategiesappliedtothelatencyreductionontactileinternet |
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1773961405696835584 |
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ri-123456789-301062020-09-20T07:50:41Z Hardware strategies applied to the latency reduction on tactile internet Silva Júnior, José Cláudio Vieira e Fernandes, Marcelo Augusto Costa Oliveira, Lucas M. Aranibar, Dennis Barrios Silva, Ivanovitch Medeiros Dantas da Oliveira, José Alberto Nicolau de Internet tátil Redução de latência Dispositivo háptico Computação reconfigurável FPGA This work proposes to present hardware strategies applied to reduce latency in the tactile internet. The motivation is to study the challenges contained in the development of the hardware associated with the tactile devices, especially issues related to the round trip latency limit of the system components. As is known, for a tactile internet environment to work desirably, it is necessary to respect a minimum limit of round trip latency. Since some tactile applications allow some human senses to interact with the machines remotely, this means that, almost always, the minimum limit of round trip latency has a time delay in the range of milliseconds. Thus, it is clear that there is a demand for tactile devices that are quite fast. In this context, three hardware proposals are presented that have the main objective to reduce the total latency produced by this type of device. The first strategy proposed for the development of hardware is to use reconfigurable computing (on FPGA) to minimize the execution time of the algorithms associated with the device. The second hardware proposal also makes use of reconfigurable computing (on FPGA). However, the hardware is designed using another type of numerical representation. Finally, the third proposal presents a tactile glove model implemented using a variety of micro processed system. Results associated with the three proposals are presented and show the viability of the strategies, presenting better performance concerning the works that were compared. Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES Este trabalho se propõe a apresentar estratégias de hardware aplicadas a redução de latência na internet tátil. A motivação é estudar os desafios contidos no desenvolvimento do hardware associado aos dispositivos táteis, especialmente questões relacionadas ao limite de latência dos componentes do sistema. Como se sabe, para que um ambiente de internet tátil funcione de forma desejável, é necessário respeitar um limite mínimo de latência associada ao envio e a volta dos dados. Uma vez que algumas aplicações táteis permitem que alguns sentidos humanos possam interagir com as máquinas de forma remota, isso faz com que, quase sempre, o limite mínimo de latência associada ao envio e a volta dos dados fique com um atraso temporal na faixa dos milissegundos. Sendo assim, percebe-se que existe uma demanda por dispositivos táteis com elevado processamento. Diante deste contexto, são apresentadas três propostas de hardware que tem como objetivo principal reduzir a latência total produzida por este tipo de dispositivo. A primeira estratégia proposta para o desenvolvimento do hardware é usar computação reconfigurável (em FPGA) para minimizar o tempo de execução dos algoritmos associados ao dispositivo. A segunda proposta de hardware também faz o uso da computação reconfigurável (em FPGA), no entanto, o hardware é projetado usando outro tipo de representação numérica. Finalmente, a terceira proposta apresenta um modelo de luva tátil implementada usando um tipo de sistema microprocessado. Resultados associados as três propostas são apresentados e mostram a viabilidade das estratégias, apresentando um desempenho superior em relação aos trabalhos apresentados na literatura. 2020-09-18T17:52:03Z 2020-09-18T17:52:03Z 2020-02-28 doctoralThesis SILVA JÚNIOR, José Cláudio Vieira e. Hardware strategies applied to the latency reduction on tactile internet. 2020. 99f. Tese (Doutorado em Engenharia Elétrica e de Computação) - Centro de Tecnologia, Universidade Federal do Rio Grande do Norte, Natal, 2020. https://repositorio.ufrn.br/jspui/handle/123456789/30106 pt_BR Acesso Aberto application/pdf Universidade Federal do Rio Grande do Norte Brasil UFRN PROGRAMA DE PÓS-GRADUAÇÃO EM ENGENHARIA ELÉTRICA E DE COMPUTAÇÃO |