Análise e projeto de um Conversor A/D Sigma Delta Incremental Multicanal de 4º Ordem
Several applications in the instrumentation field require signal acquisition systems with medium conversion rate and medium to high resolution, among them are the Multielectrode Matrices (MEA). The MEA manufactured on CMOS standard technology integrated circuits have allowed the study of several ty...
Gorde:
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| Beste egile batzuk: | |
| Formatua: | doctoralThesis |
| Hizkuntza: | pt_BR |
| Argitaratua: |
Brasil
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| Gaiak: | |
| Sarrera elektronikoa: | https://repositorio.ufrn.br/jspui/handle/123456789/26770 |
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| Gaia: | Several applications in the instrumentation field require signal acquisition systems
with medium conversion rate and medium to high resolution, among them are the Multielectrode Matrices (MEA). The MEA manufactured on CMOS standard technology integrated circuits have allowed the study of several types of cell cultures, allowing the
stimulation and recording of electrical activities of the cells in vitro. As the CMOS technology advances, the biomedical signal processing is suitably done in digital domain.
Therefore, basic blocks such as Analog to Digital Converters (ADC) are essential to realize the interface in the mixed signal systems. In this way, this work proposes the design
of an ADC to be applied in the multichannel biomedical signal acquisition systems, following the top-down approach for the Integrated Circuit design (IC). The architecture
of the ADC consists of an Incremental Sigma Delta Converter (IΣ∆), which combines
the high-precision characteristic of the traditional Σ∆ modulators with the advantage of
the sample-by-sample conversion of the Nyquist converters, making it suitable for multichannel time-multiplexed applications. The modulator and digital filter which compose
the IΣ∆ ADC consist of the single-loop Cascaded-Integrator FeedForward (CIFF) and
Cascade-of-Integrator (CoI) topologies respectively, both fourth-order. The modulator
was implemented in Discrete Time (DT), using the Switched Capacitor technique (SC).
The circuits were designed using TSMC 0.18 µm CMOS technology and the results were
obtained from post-layout, PVT and Monte Carlo simulations. |
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