An aI based tool for networks-on-chip design space exploration
With the increasing number of cores in Systems on Chip (SoCs), bus architectures have suffered some limitations regarding performance. As applications demand more bandwidth and lower latencies, busses could not comply with such requirements due to longer wires and increased capacitancies. Facing...
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| Format: | masterThesis |
| Language: | por |
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Brasil
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| Online Access: | https://repositorio.ufrn.br/jspui/handle/123456789/25937 |
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