An aI based tool for networks-on-chip design space exploration

With the increasing number of cores in Systems on Chip (SoCs), bus architectures have suffered some limitations regarding performance. As applications demand more bandwidth and lower latencies, busses could not comply with such requirements due to longer wires and increased capacitancies. Facing...

Cur síos iomlán

Sábháilte in:
Sonraí bibleagrafaíochta
Príomhchruthaitheoir: Silva, Jefferson Igor Duarte
Rannpháirtithe: Kreutz, Márcio Eduardo
Formáid: Dissertação
Teanga:por
Foilsithe / Cruthaithe: Brasil
Ábhair:
Network-on-chip
Artificial intelligence
Design space exploration
CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO
Rochtain ar líne:https://repositorio.ufrn.br/jspui/handle/123456789/25937
Clibeanna: Cuir clib leis
Níl clibeanna ann, Bí ar an gcéad duine le clib a chur leis an taifead seo!
id ri-123456789-25937
record_format dspace
spelling ri-123456789-259372019-01-30T07:34:18Z An aI based tool for networks-on-chip design space exploration Silva, Jefferson Igor Duarte Kreutz, Márcio Eduardo Matos, Débora da Silva Motta Pereira, Monica Magalhães Network-on-chip Artificial intelligence Design space exploration CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO With the increasing number of cores in Systems on Chip (SoCs), bus architectures have suffered some limitations regarding performance. As applications demand more bandwidth and lower latencies, busses could not comply with such requirements due to longer wires and increased capacitancies. Facing this scenario, Networks-on-Chip (NoCs) emerged as a way to overcome limitations found in bus-based systems. NoCs are composed of a set of routers and communication links. Each component has its own characteristics. Fully exploring all possible NoC characteristics settings is unfeasible due to the huge design space to cover. Therefore, some methods to speed up this process are needed. In this work, we propose the usage of Artificial Intelligence techniques to optimize NoC architectures. This is accomplished by developing an AI based tool to explore the design space in terms of area, latency, and power prediction for different NoCs components configuration. Up to now, nine classifiers were evaluated. To evaluate this tool, tests were performed on Audio/Video applications with Bit-Reversal, Butterfly, Uniform, Perfect Shuffle, and Transpose Matrix traffic patterns, with four different communication requirements. The first result show an accuracy up to 88% and to 100%, using Decision Trees to predict latency and area/power values, respectively. As second step, a Genetic Algorithm was applied to explore the design space and the reached results ratify that the solutions found are valid and adequate to the constraints of the designer. 2018-10-04T21:23:30Z 2018-10-04T21:23:30Z 2018-08-29 masterThesis SILVA, Jefferson Igor Duarte. An aI based tool for networks-on-chip design space exploration. 2018. 91f. Dissertação (Mestrado em Sistemas e Computação) - Centro de Ciências Exatas e da Terra, Universidade Federal do Rio Grande do Norte, Natal, 2018. https://repositorio.ufrn.br/jspui/handle/123456789/25937 por Acesso Aberto application/pdf Brasil UFRN PROGRAMA DE PÓS-GRADUAÇÃO EM SISTEMAS E COMPUTAÇÃO
institution Repositório Institucional
collection RI - UFRN
language por
topic Network-on-chip
Artificial intelligence
Design space exploration
CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO
spellingShingle Network-on-chip
Artificial intelligence
Design space exploration
CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO
Silva, Jefferson Igor Duarte
An aI based tool for networks-on-chip design space exploration
description With the increasing number of cores in Systems on Chip (SoCs), bus architectures have suffered some limitations regarding performance. As applications demand more bandwidth and lower latencies, busses could not comply with such requirements due to longer wires and increased capacitancies. Facing this scenario, Networks-on-Chip (NoCs) emerged as a way to overcome limitations found in bus-based systems. NoCs are composed of a set of routers and communication links. Each component has its own characteristics. Fully exploring all possible NoC characteristics settings is unfeasible due to the huge design space to cover. Therefore, some methods to speed up this process are needed. In this work, we propose the usage of Artificial Intelligence techniques to optimize NoC architectures. This is accomplished by developing an AI based tool to explore the design space in terms of area, latency, and power prediction for different NoCs components configuration. Up to now, nine classifiers were evaluated. To evaluate this tool, tests were performed on Audio/Video applications with Bit-Reversal, Butterfly, Uniform, Perfect Shuffle, and Transpose Matrix traffic patterns, with four different communication requirements. The first result show an accuracy up to 88% and to 100%, using Decision Trees to predict latency and area/power values, respectively. As second step, a Genetic Algorithm was applied to explore the design space and the reached results ratify that the solutions found are valid and adequate to the constraints of the designer.
author2 Kreutz, Márcio Eduardo
author_facet Kreutz, Márcio Eduardo
Silva, Jefferson Igor Duarte
format masterThesis
author Silva, Jefferson Igor Duarte
author_sort Silva, Jefferson Igor Duarte
title An aI based tool for networks-on-chip design space exploration
title_short An aI based tool for networks-on-chip design space exploration
title_full An aI based tool for networks-on-chip design space exploration
title_fullStr An aI based tool for networks-on-chip design space exploration
title_full_unstemmed An aI based tool for networks-on-chip design space exploration
title_sort ai based tool for networks-on-chip design space exploration
publisher Brasil
publishDate 2018
url https://repositorio.ufrn.br/jspui/handle/123456789/25937
work_keys_str_mv AT silvajeffersonigorduarte anaibasedtoolfornetworksonchipdesignspaceexploration
AT silvajeffersonigorduarte aibasedtoolfornetworksonchipdesignspaceexploration
_version_ 1773967156276363264

Míreanna comhchosúla