An aI based tool for networks-on-chip design space exploration
With the increasing number of cores in Systems on Chip (SoCs), bus architectures have suffered some limitations regarding performance. As applications demand more bandwidth and lower latencies, busses could not comply with such requirements due to longer wires and increased capacitancies. Facing...
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| Natura: | Dissertação |
| Lingua: | por |
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| Accesso online: | https://repositorio.ufrn.br/jspui/handle/123456789/25937 |
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| Riassunto: | With the increasing number of cores in Systems on Chip (SoCs), bus architectures have
suffered some limitations regarding performance. As applications demand more bandwidth
and lower latencies, busses could not comply with such requirements due to longer wires
and increased capacitancies. Facing this scenario, Networks-on-Chip (NoCs) emerged as
a way to overcome limitations found in bus-based systems. NoCs are composed of a set
of routers and communication links. Each component has its own characteristics. Fully
exploring all possible NoC characteristics settings is unfeasible due to the huge design
space to cover. Therefore, some methods to speed up this process are needed. In this
work, we propose the usage of Artificial Intelligence techniques to optimize NoC architectures.
This is accomplished by developing an AI based tool to explore the design space in
terms of area, latency, and power prediction for different NoCs components configuration.
Up to now, nine classifiers were evaluated. To evaluate this tool, tests were performed
on Audio/Video applications with Bit-Reversal, Butterfly, Uniform, Perfect Shuffle, and
Transpose Matrix traffic patterns, with four different communication requirements. The
first result show an accuracy up to 88% and to 100%, using Decision Trees to predict
latency and area/power values, respectively. As second step, a Genetic Algorithm was
applied to explore the design space and the reached results ratify that the solutions found
are valid and adequate to the constraints of the designer. |
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