Proposta de implementação dos algoritmos de hash MD5 e SHA-1 em hardware reconfigurável
This work proposes two Application Specific System Processor (ASSP), one to the MD5 algorithm and other to the SHA-1 algorithm implemented on Field Programmable Gate Array (FPGA) Xilinx Virtex 6 xc6vlx240t-1ff1156. The throughput and the occupied area were analyzed for several implementations on...
Saved in:
Main Author: | |
---|---|
Other Authors: | |
Format: | masterThesis |
Language: | por |
Published: |
Brasil
|
Subjects: | |
Online Access: | https://repositorio.ufrn.br/jspui/handle/123456789/25779 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|