Design of cost-efficient interconnect processing units : Spidergon STNoC /

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Autor principal: Coppola, Marcello.
Formato: Livro
Publicado em:
Assuntos:
ST Microprocessadores.
Redes em chip.
Microprocessadores.
Endereço do item:https://app.bczm.ufrn.br/home/#/item/163246
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spelling oai:localhost:123456789-2057622022-11-30T17:13:03Z Design of cost-efficient interconnect processing units : Spidergon STNoC / Coppola, Marcello. ST Microprocessadores. Redes em chip. Microprocessadores. 1 2022-10-11T09:35:57Z 2022-10-11T09:35:57Z 2009. Livro 004.722 D457 9781420044713 (hardback : alk. paper) 163246 https://app.bczm.ufrn.br/home/#/item/163246 https://app.bczm.ufrn.br/home/#/item/163246
institution Acervo SISBI
collection SIGAA
topic ST Microprocessadores.
Redes em chip.
Microprocessadores.
spellingShingle ST Microprocessadores.
Redes em chip.
Microprocessadores.
Coppola, Marcello.
Design of cost-efficient interconnect processing units : Spidergon STNoC /
description
format Livro
author Coppola, Marcello.
author_facet Coppola, Marcello.
author_sort Coppola, Marcello.
title Design of cost-efficient interconnect processing units : Spidergon STNoC /
title_short Design of cost-efficient interconnect processing units : Spidergon STNoC /
title_full Design of cost-efficient interconnect processing units : Spidergon STNoC /
title_fullStr Design of cost-efficient interconnect processing units : Spidergon STNoC /
title_full_unstemmed Design of cost-efficient interconnect processing units : Spidergon STNoC /
title_sort design of cost-efficient interconnect processing units : spidergon stnoc /
publishDate 2022
url https://app.bczm.ufrn.br/home/#/item/163246
work_keys_str_mv AT coppolamarcello designofcostefficientinterconnectprocessingunitsspidergonstnoc
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